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agilent hcpl-9000/-0900, -9030/-0930, hcpl-9031/-0931, -900j/-090j, HCPL-901J/-091j, -902j/-092j high speed digital isolators data sheet description the hcpl-90xx and hcpl-09xx cmos digital isolators feature high speed performance and excellent transient immunity specifications. the symmetric magnetic coupling barrier gives these devices a typical pulse width distortion of 2 ns, a typical propagation delay skew of 4 ns and 100 mbaud data rate, making them the industry s fastest digital isolators. the single channel digital isola- tors (hcpl-9000/-0900) features an active-low logic output enable. the dual channel digital isolators are configured as unidirectional (hcpl-9030/-0930) and bi- directional (hcpl-9031/-0931), operating in full duplex mode making it ideal for digital fieldbus applications. the quad channel digital isola- tors are configured as unidirec- features ? +3.3v and +5v ttl/cmos compatible ? 3 ns max. pulse width distortion ? 6 ns max. propagation delay skew ? 15 ns max. propagation delay ? high speed: 100 mbd ? 15 kv/ s min. common mode rejection ? tri-state output (hcpl-9000/-0900) ? 2500 v rms isolation ? ul1577 and iec 61010-1 approved applications ? digital fieldbus isolation ? multiplexed data transmission ? computer peripheral interface ? high speed digital systems ? isolated data interfaces ? logic level shifting tional (hcpl-900j/-090j), two channels in one direction and two channels in opposite direc- tion (HCPL-901J/-091j), and one channel in one direction and three channels in opposite direction (hcpl-902j/-092j). these high channel density make them ideally suited to isolating data conversion devices, parallel buses and peripheral interfaces. they are available in 8-pin pdip, 8-pin gull wing, 8-pin soic packages, and 16 C pin soic narrow-body and wide-body packages. they are specified over the temperature range of -40 c to +100 c. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd.
2 selection guide device number channel configuration package hcpl-9000 single 8-pin dip (300 mil) hcpl-0900 single 8-pin small outline hcpl-9030 dual 8-pin dip (300 mil) hcpl-0930 dual 8-pin small outline hcpl-9031 dual, bi-directional 8-pin dip (300 mil) hcpl-0931 dual, bi-directional 8-pin small outline hcpl-900j quad 16-pin small outline, wide body hcpl-090j quad 16-pin small outline, narrow body HCPL-901J quad, 2/2, bi-directional 16-pin small outline, wide body hcpl-091j quad, 2/2, bi-directional 16-pin small outline, narrow body hcpl-902j quad, 1/3, bi-directional 16-pin small outline, wide body hcpl-092j quad, 1/3, bi-directional 16-pin small outline, narrow body ordering information specify part number followed by option number (if desired). examples: hcpl-90xx- xxxx xxxx: no option = 300 mil pdip-8 package, 50 units per tube. 300 = gull wing surface mount option, 50 units per tube. 500 = tape and reel packaging option, 1000 units per reel. xxxe = lead-free option. hcpl-09xx- xxxx xxxx: no option = so-8 package, 100 units per tube. 500 = tape and reel packaging option, 1500 units per reel. xxxe = lead-free option. hcpl-90xj- xxxx xxxx: no option = wide body soic-16 package, 50 units per tube. 500 = tape and reel packaging option, 1000 units per reel. xxxe = lead-free option. hcpl-09xj- xxxx xxxx: no option = narrow body soic-16 package, 50 per tube. 500 = tape and reel packaging option, 1000 units per reel. xxxe = lead-free option.
3 pin description symbol description v dd1 power supply 1 v dd2 power supply 2 in x logic input signal out x logic output signal gnd 1 power supply ground 1 gnd 2 power supply ground 2 v oe logic output enable (single channel), active low nc not connected functional diagrams truth table in 1 v oe out 1 lll hl h lhz hhz v dd1 in 1 nc gnd 1 gnd 2 out 1 v dd2 v oe 8 7 6 5 1 2 3 4 galvanic isolation hcpl-9000/0900 single channel dual channel v dd1 in 1 in 2 gnd 1 gnd 2 out 2 v dd2 out 1 8 7 6 5 1 2 3 4 galvanic isolation hcpl-9030/0930 quad channel 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 v dd1 gnd 1 in 1 in 2 in 3 in 4 nc gnd 1 gnd 2 nc out 4 out 3 out 2 out 1 gnd 2 v dd2 galvanic isolation hcpl-900j/-090j 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 v dd1 gnd 1 in 1 in 2 out 3 out 4 nc gnd 1 gnd 2 nc in 4 in 3 out 2 out 1 gnd 2 v dd2 galvanic isolation HCPL-901J/-091j 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 v dd1 gnd 1 in 1 in 2 in 3 out 4 nc gnd 1 gnd 2 nc in 4 out 3 out 2 out 1 gnd 2 v dd2 galvanic isolation hcpl-902j/-092j v dd1 in 1 out 2 gnd 1 gnd 2 in 2 v dd2 out 1 8 7 6 5 1 2 3 4 galvanic isolation hcpl-9031/0931
4 package outline drawings hcpl-9000, hcpl-9030 and hcpl-9031 standard dip packages hcpl-9000, hcpl-9030 and hcpl-9031 gull wing surface mount option 300 0.030 (0.762) 0.045 (1.143) 0.370 (9.400) 0.390 (9.900) 0.240 (6.100) 0.260 (6.600) 87 6 5 4 3 2 1 0.045 (1.143) 0.065 (1.651) 0.120 (3.048) 0.150 (3.810) 0.047 (1.194) 0.070 (1.778) 0.040 (1.016) 0.047 (1.194) 0.370 (9.398) 0.390 (9.906) 0.190 (4.826) 0.015 (0.381) 0.025 (0.635) 0.025 (0.632) 0.035 (0.892) 0.030 (0.760) 0.056 (1.400) 0.015 (0.385) 0.035 (0.885) 0.290 (7.370) 0.310 (7.870) 0.370 (9.400) 0.390 (9.900) pad location (for reference only) typ. 12 nom. 0.008 (0.203) 0.013 (0.330) 0.100 (2.540) bsc dimensions inches (millimeters) lead coplanarity = 0.004 inches ( 0.10 mm ) min max 5 6 7 8 4 3 2 1 dimensions: inches (millimeters) min max 0.120 (3.048) 0.150 (3.810) 0.240 (6.096) 0.260 (6.604) 0.015 (0.381) 0.035 (0.889) 0.55 (1.397) 0.65 (1.651) 0.008 (0.203) 0.015 (0.381) 3 8 0.030 (0.762) 0.045 (1.143) 0.015 (0.380) 0.023 (0.584) 0.045 (1.143) 0.065 (1.651) 0.090 (2.286) 0.110 (2.794) 0.370 (9.398) 0.400 (10.160) 0.290 (7.366) 0.310 (7.874) 0.300 (7.620) 0.370 (9.398)
5 87 65 4 3 2 1 0.228 (5.80) 0.244 (6.20) 0.189 (4.80) 0.197 (5.00) 0.150 (3.80) 0.157 (4.00) 0.013 (0.33) 0.020 (0.51) 0.040 (1.016) 0.060 (1.524) 0.004 (0.10) 0.010 (0.25) 0.054 (1.37) 0.069 (1.75) 0.016 (0.40) 0.050 (1.27) 0.008 (0.19) 0.010 (0.25) 0.010 (0.25) 0.020 (0.50) x 45 0 8 dimensions: inches (millimeters) min max hcpl-0900, hcpl-0930 and hcpl-0931 small outline so-8 package hcpl-900j, HCPL-901J and hcpl-902j wide body soic-16 package 1 pin 1 indent 8 7 typ 0.394 (10.007) 0.419 (10.643) 0.397 (10.084) 0.413 (10.490) 0.291 (7.391) 0.299 (7.595) 0.013 (0.330) 0.020 (0.508) 0.040 (1.016) 0.060 (1.524) 0.080 (2.032) 0.100 (2.54) 0.092 (2.337) 0.104 (2.642) 0.004 (0.1016) 0.011 (0.279) 0.016 (0.40) 0.050 (1.27) 0.010 (0.254) 0.020 (0.508) 0.287 (7.290) 0.297 (7.544) x 45 0 C 8 typ 7 typ 0.009 (0.229) 0.012 (0.305) dimensions: inches (millimeters) min max
6 hcpl-090j, hcpl-091j and hcpl-092j narrow body soic-16 package 1 pin 1 indent 8 0.228 (5.791) 0.244 (6.197) 0.386 (9.802) 0.394 (9.999) 0.152 (3.861) 0.157 (3.988) 0.013 (0.330) 0.020 (0.508) 0.040 (1.016) 0.060 (1.524) 0.050 (1.270) 0.060 (1.524) 0.054 (1.372) 0.068 (1.727) 0.004 (0.102) 0.010 (0.249) 0.016 (0.406) 0.050 (1.270) 0.010 (0.245) 0.020 (0.508) 0.008 (0.191) 0.010 (0.249) x 45 0 C 8 typ dimensions: inches (millimeters) min max package characteristics parameter symbol min. typ. max. units test conditions capacitance (input-output) [1] c i-o pf f = 1 mhz single channel 1.1 dual channel 2.0 quad channel 4.0 thermal resistance jct c/w thermocouple located at 8-pin pdip 150 center underside of package 8-pin soic 240 package power dissipation p pd mw 8-pin pdip 150 8-pin soic 150 notes: 1. single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. quad channel devi ces are considered two-terminal devices: pins 1-8 shorted and pins 9-16 shorted. this product has been tested for electrostatic sensitivity to the limits stated in the specifications. however, agilent recomme nds that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inappropriate handling or storage could range from performan ce degradation to complete failure.
7 insulation and safety related specifications parameters condition min. typ. max. units barrier impedance ? ||pf single channel >10 14 || 3 dual channel >10 14 || 3 quad channel >10 14 || 7 creepage distance (external) mm 8-pin pdip 7.036 8-pin soic 4.026 16-pin soic narrow body 4.026 16-pin soic wide body 8.077 leakage current 240 v rms 0.2 a 60 hz absolute maximum ratings parameters symbol min. max. units storage temperature t s C55 175 c ambient operating temperature [1] t a C55 125 c supply voltage v dd1 , v dd2 C0.5 7 v input voltage v in C0.5 v dd1 +0.5 v voltage output enable (hcpl-9000/-0900) v oe C0.5 v dd2 +0.5 v output voltage v out C0.5 v dd2 +0.5 v output current drive i out 10 ma lead solder temperature (10s) 260 c esd 2 kv human body model notes: 1. absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. it do es not guarantee performance. recommended operating conditions parameters symbol min. max. units ambient operating temperature t a C 40 100 c supply voltage v dd1 , v dd2 3.0 5.5 v logic high input voltage v ih 2.4 v dd1 v logic low input voltage v il 0 0.8 v input signal rise and fall times t ir , t if 1 s this product has been tested for electrostatic sensitivity to the limits stated in the specifications. however, agilent recomme nds that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inappropriate handling or storage could range from performan ce degradation to complete failure.
8 electrical specifications test conditions that are not specified can be anywhere within the recommended operating range. all typical specifications are at t a =+25 c, v dd1 = v dd2 = +3.3 v. parameter symbol min. typ. max. units test conditions quiescent supply current 1 i dd1 ma v in = 0v hcpl-9000/-0900 0.008 0.01 hcpl-9030/-0930 0.008 0.01 hcpl-9031/-0931 1.5 2.0 hcpl-900j/-090j 0.016 0.02 HCPL-901J/-091j 3.3 4.0 hcpl-902j/-092j 1.5 2.0 quiescent supply current 2 i dd2 ma v in = 0v hcpl-9000/-0900 3.3 4.0 hcpl-9030/-0930 3.3 4.0 hcpl-9031/-0931 1.5 2.0 hcpl-900j/-090j 5.5 8.0 HCPL-901J/-091j 3.3 4.0 hcpl-902j/-092j 3.0 6.0 logic input current i in -10 10 a logic high output voltage v oh v dd2 C 0.1 v dd2 vi out = -20 a, v in =v ih 0.8 * v dd2 v dd2 C 0.5 v i out = -4 ma, v in =v ih logic low output voltage v ol 0 0.1 v i out = 20 a, v in =v il 0.5 0.8 v i out = 4 ma, v in =v il switching specifications maximum data rate 100 110 mbd c l = 15 pf clock frequency fmax 50 mhz propagation delay time to logic t phl 12 18 ns low output propagation delay time tologic t plh 12 18 ns high output pulse width t pw 10 ns pulse width distortion [1] |pwd| 2 3 ns |t phl C t plh | propagation delay skew [2] t psk 46ns output rise time (10 C 90%) t r 24ns output fall time (10 C 90%) t f 24ns propagation delay enable to output (single channel) high to high impedance t phz 35ns low to high impedance t plz 35ns high impedance to high t pzh 35ns high impedance to low t pzl 35ns channel-to-channel skew t csk 23ns (dual and quad channels) common mode transient immunity |cm h | 15 18 kv/ sv cm = 1000v (output logic high or logic low) [3] |cm l | notes: 1. pwd is defined as |t phl -t plh |. %pwd is equal to the pwd divided by the pulse width. 2. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at 25 c. 3. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v out > 0.8v dd2 . cm l is the maximum common mode input voltage that can be sustained while maintaining v out < 0.8v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. this product has been tested for electrostatic sensitivity to the limits stated in the specifications. however, agilent recomme nds that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inappropriate handling or storage could range from performan ce degradation to complete failure.
9 electrical specifications test conditions that are not specified can be anywhere within the recommended operating range. all typical specifications are at t a =+25 c, v dd1 = v dd2 = +5.0 v. parameter symbol min. typ. max. units test conditions quiescent supply current 1 i dd1 ma v in = 0v hcpl-9000/-0900 0.012 0.018 hcpl-9030/-0930 0.012 0.018 hcpl-9031/-0931 2.5 3.0 hcpl-900j/-090j 0.024 0.036 HCPL-901J/-091j 5.0 6.0 hcpl-902j/-092j 2.5 3.0 quiescent supply current 2 i dd2 ma v in = 0v hcpl-9000/-0900 5.0 6.0 hcpl-9030/-0930 5.0 6.0 hcpl-9031/-0931 2.5 3.0 hcpl-900j/-090j 8.0 12.0 HCPL-901J/-091j 5.0 6.0 hcpl-902j/-092j 6.0 9.0 logic input current i in -10 10 a logic high output voltage v oh v dd2 C 0.1 v dd2 vi out = -20 a, v in =v ih 0.8 * v dd2 v dd2 C 0.5 v i out = -4 ma, v in =v ih logic low output voltage v ol 0 0.1 v i out = 20 a, v in =v il 0.5 0.8 v i out = 4 ma, v in =v il switching specifications maximum data rate 100 110 mbd c l = 15 pf clock frequency fmax 50 mhz propagation delay time to logic t phl 10 15 ns low output propagation delay time to logic t plh 10 15 ns high output pulse width t pw 10 ns pulse width distortion [1] |pwd| 2 3 ns |t phl C t plh | propagation delay skew [2] t psk 46ns output rise time (10 C 90%) t r 13ns output fall time (10 C 90%) t f 13ns propagation delay enable to output (single channel) high to high impedance t phz 35ns low to high impedance t plz 35ns high impedance to high t pzh 35ns high impedance to low t pzl 35ns channel-to-channel skew t csk 23ns (dual and quad channels) common mode transient immunity |cm h | 15 18 kv/ sv cm = 1000v (output logic high or logic low) [3] |cm l | notes: 1. pwd is defined as |t phl -t plh |. %pwd is equal to the pwd divided by the pulse width. 2. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at 25 c. 3. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v out > 0.8v dd2 . cm l is the maximum common mode input voltage that can be sustained while maintaining v out < 0.8v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. this product has been tested for electrostatic sensitivity to the limits stated in the specifications. however, agilent recomme nds that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inappropriate handling or storage could range from performan ce degradation to complete failure.
10 applications information power consumption the hcpl-90xx and hcpl-09xx cmos digital isolators achieves low power consumption from the manner by which they transmit data across isolation barrier. by detecting the edge transitions of the input logic signal and con- verting this to a narrow current pulse, which drives the isolation barrier, the isolator then latches the input logic state in the output latch. since the current pulses are narrow, about 2.5 ns wide, the power consumption is indepen- dent of mark-to-space ratio and solely dependent on frequency. the approximate power supply current per channel is: i(input) = 40(f/fmax)(1/4) ma where f = operating frequency, fmax = 50 mhz. signal status on start-up and shut down to minimize power dissipation, the input signals to the channels of hcpl-90xx and hcpl-09xx digital isolators are differenti- ated and then latched on the output side of the isolation barrier to reconstruct the signal. this could result in an ambigu- ous output state depending on power up, shutdown and power loss sequencing. therefore, the designer should consider the inclusion of an initialization signal in this start-up circuit. bypassing and pc board layout the hcpl-90xx and hcpl-09xx digital isolators are extremely easy to use. no external interface circuitry is required because the isolators use high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 1, the only external components required for proper operation are two 47 nf ceramic capacitors for decoupling the power supplies. for each capaci- tor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 2 illustrates the recommended printed circuit board layout for the hcpl-9000 or hcpl-0900. for data rates in excess of 10mbd, use of ground planes for both gnd 1 and gnd 2 is highly recommended. figure 1. functional diagram of single channel hcpl-0900 or hcpl-0900. 1 2 3 45 6 7 8 v dd1 in 1 c1 c2 note: c1, c2 = 47 nf ceramic capacitors nc gnd 1 v dd2 out 1 gnd 2 hcpl-9000 or hcpl-0900 v oe figure 2. recommended printed circuit board layout. c2 v dd2 out 1 gnd 2 v dd1 gnd 1 in 1 c1 v oe hcpl-9000 or hcpl-0900
11 propagation delay, pulse width distortion and propagation delay skew propagation delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in figure 3. the propagation delay from low to high, t plh , is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low, t phl , is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. figure 3. timing diagrams to illustrate propagation delay, t plh and t phl . figure 4. timing diagrams to illustrate propagation delay skew. v in v out v out v in t psk 50% 50% 2.5 v cmos 2.5 v cmos pulse width distortion, pwd, is the difference between t phl and t plh and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20 C 30% of the minimum pulse width is tolerable. propagation delay skew, t psk , and channel-to-channel skew, t csk , are critical parameters to consider in parallel data trans- mission applications where synchronization of signals on parallel data lines is a concern. if the parallel data is being sent through channels of the digital isolators, differences in propaga- tion delays will cause the data to arrive at the outputs of the digital isolators at different times. if this difference in propagation delay is large enough, it will limit the maxi- mum transmission rate at which parallel data can be sent through the digital isolators. t psk is defined as the difference between the minimum and maximum propagation delays, either t plh or t phl , among two or more devices which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operat- ing temperature). t csk is defined as the difference between the minimum and maximum propaga- tion delays, either t plh or t phl , among two or more channels within a single device (applicable to dual and quad channel de- vices) which are operating under the same conditions. as illustrated in figure 4, if the inputs of two or more devices are switched either on or off at the same time, t psk is the difference between the minimum propaga- tion delay, either t plh or t phl , and the maximum propagation delay, either t plh or t phl . as mentioned earlier, t psk , can determine the maximum parallel data transmission rate. figure 5 shows the timing diagram of a typical parallel data transmission application with both the clock and data lines being sent through the digital isolators. the figure shows data and clock signals at the inputs and outputs of the digital isolators. in this case, the data is clocked off the rising edge of the clock. figure 5. parallel data transmission. data data inputs clock outputs clock t psk t psk input output 5 v cmos 2.5 v cmos 0 v v oh v ol v out v in t plh t phl 50% 10% 90% 90% 10%
propagation delay skew repre- sents the uncertainty of where an edge might be after being sent through a digital isolator. figure 5 shows that there will be uncer- tainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through digital isolators in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to figure 6. timing diagrams to illustrate the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for hcpl-9000 or hcpl-0900. ensure that any additional uncertainty in the rest of the circuit does not cause a problem. figure 6 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for hcpl-9000 or hcpl-0900. 50% 50% 90% 10% 10% 90% v in v out v oe t pw t plz t pzh t phz t pzl t f t r t pw minimum pulse width t phz propagation delay, high to high impedance t plz propagation delay, low to high impedance t pzl propagation delay, high impedance to low t pzh propagation delay, high impedance to high t r rise time t f fall time www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (65) 6756 2394 india, australia, new zealand: (65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (65) 6755 2044 taiwan: (65) 6755 1843 data subject to change. copyright ? 2004 agilent technologies, inc. obsoletes 5988-5626en february 24, 2004 5989-0803en

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